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CRD42L52
5. PERFORMANCE PLOTS
Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band-
width is 20 Hz to 20 kHz (unweighted); VA=VD=VA_HP=1.8 V; Sample Frequency = 48 kHz; HP test load:
R L = 10 k ? .
-50
-52.5
-55
-57.5
-60
-62.5
-65
-67.5
-70
+5
+4.5
+4
+3.5
+3
+2.5
+2
+1.5
+1
d
B
F
S
-72.5
-75
-77.5
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
d
B
F
S
+0.5
-0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-100
20
50
100
200
500
1k
2k
5k
10k
20k
-5
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 9. Dynamic Range - Line In to S/PDIF Out
-50
Hz
Figure 10. Freq. Resp. - Line In to S/PDIF Out
+0
-52.5
-10
-55
-57.5
-20
-60
-30
-62.5
-65
-67.5
-70
* (Note 1)
-40
-50
d
B
F
S
-72.5
-75
-77.5
d
B
r
A
-60
-70
-80
-80
-82.5
-90
-85
-100
-87.5
-90
-92.5
-95
-97.5
-110
-120
-130
-100
20
50
100
200
500
1k
2k
5k
10k
20k
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 11. THD + N - Line In to S/PDIF Out
Hz
Figure 12. FFT - S/PDIF In to HP Out @ 0 dBFS
Notes:
1. The total harmonic distortion + noise (THD+N) performance of the ADC in the CS42L52 is determined by
the value of the capacitor on the FILT+ pin. Larger capacitor values yield significant improvement in THD+N
at low frequencies. A 1 uF capacitor was used to make the performance measurement in Figure 12 .
DS680RD1
15
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